This year’s IEEE International Electronic Equipment Conference (IEDM), chip giant Intel released a road map for manufacturing process expansion in the next ten years from 2019 to 2029, including launch in 2029 1.4 nano meter manufacturing process.
1.4 nanometer process by 2029
Intel expects its manufacturing process node technology to maintain a two-year leap forward, starting with the 10-nano-meter process in 2019 and moving to 7-nano meter EUV (extreme ultraviolet lithography) in 2021, then adopting 5-nano-meter in 2023 and 2025 in 3 Nanometers, 2 nanometers in 2027, and finally 1.4 nanometers in 2029. This is the first time that Intel mentioned the 1.4 nanometer process, which is equivalent to the position occupied by 12 silicon atoms, so it also confirmed the direction of Intel’s development.
It may be worth noting that at this year’s IEDM conference, some of the talks involved technology with a process size of 0.3 nanometers, using so-called “2D self-assembly” materials. Although it is not the first time to hear about such a process, it is the first time someone has mentioned it in the field of silicon chip manufacturing. Obviously, Intel (and its partners) have many problems to overcome.
Technology iterations and backports
Between the two generations of process nodes, Intel will introduce iterative versions of the + and ++ processes to extract as much optimized performance from each node as possible. The only exception is the 10nm process, which is already in the 10+ version stage, so we will see 10 ++ and 10 +++ versions in 2020 and 2021, respectively. Intel believes that they can do this every year, but also have overlapping teams to ensure that one complete process node can overlap with another.
What’s interesting about Intel’s roadmap is that it mentions “back porting.” This is a process node capability that must be considered in chip design. Although Intel states that they are separating the chip design from the process node technology, at some point, the process node process is locked in order to begin the layout in silicon, especially when it enters the mask creation, so in the specific It’s not easy to implement.
However, the road map shows that Intel will allow a workflow where any first-generation 7-nano meter design can be back ported to the 10 ++ version and any first-generation 5nm design can be back ported to 7+ + Version, then 3nm backport to 5 ++, 2nm backport to 3 ++, and so on. Some people may say that the date limit of this road map may not be so strict. We have seen that Intel’s 10-nano meter technology takes a long time to mature, so we expect the company to focus on the main process technology within two years The pace of updates on the node at a pace of one year seems too optimistic.
Note that when it comes to Intel, this is not the first time a “backport” hardware design is mentioned. Because Intel’s 10-nano meter process technology is currently in the delay stage, there are widespread rumors that Intel’s future CPU micro architecture designs may eventually use the very successful 14-nano meter process.
R & D efforts
Generally, with the development of process nodes, different teams need to be responsible for the work of each node. This roadmap illustrates that Intel is currently developing its 10 ++ optimization and 7nm series processes. The idea is that from a design point of view, each generation of the + version can be easily implemented, as this number represents the full node advantage.
Interestingly, we see that Intel’s 7nm process is developed based on the 10 ++ version, and Intel believes that the future 5nm process will also be based on the 7nm process design, and 3nm will be based on the 5nm design. There is no doubt that certain optimizations per + / ++ iteration will be ported to future designs when needed.
In this roadmap, we see that Intel’s 5nm process is currently in the definition stage. At this IEDM conference, there was a lot of discussion about the 5nm process, so some of the improvements (such as manufacturing, materials, consistency, etc.) will eventually be applied to Intel’s 5nm process, depending on which design companies they work with Cooperation (historically applied materials company).
In addition to 5nm process development, we can also take a look at Intel’s 3nm, 2nm and 1.4nm process blueprints. The company is currently in path finding mode. Looking ahead, Intel is considering new materials and new transistor designs. It is also worth pointing out that based on the new road map, Intel clearly still believes in Moore’s Law