3nm chip area is 35% smaller than 5nm products, power consumption is reduced by 50%

Samsung ’s Vice President Lee Jae-hyun visited the Hwaseong Semiconductor Plant in Gyeonggi, South Korea, which is developing “the world ’s first 3-nanometer semiconductor process,” and heard a report on 3-nanometer process technology. The presidential group discussed the next-generation semiconductor strategy.

It is understood that Samsung Electronics plans to use the extreme ultraviolet lithography (EUV) process to increase its market share in fine engineering below 7 nanometers. The 3 nanometer semiconductor process plan was first applied to Samsung’s foundry project. Samsung plans to achieve the world’s earliest mass production of 3 nanometer chips in the second half of next year.

Samsung Electronics will use a new generation process “GAA” that is different from other projects in the latest 3 nanometer project. Samsung Electronics ’department in charge of the semiconductor industry said that the area of ​​3 nanometer chips based on GAA technology can be reduced by more than 35%, the power consumption is reduced by 50%, and the processing speed can be increased by about 30%.

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